1. Field of the Invention
The present invention relates to semiconductor devices and fabrication methods thereof, and, more particularly, to a semiconductor device having a low-k dielectric layer and a fabrication method thereof.
2. Description of Related Art
Generally, flip-chip mounting involves electrically connecting an active surface of a chip (or other semiconductor structures) to one surface of a substrate through a plurality of metal bumps, and mounting a plurality of solder balls serving as I/O connections on the other surface of the substrate, as disclosed in U.S. Pat. No. 6,008,534, U.S. Pat. No. 6,225,704, and U.S. Pat. No. 6,372,544. The flip-chip mounting technology leads to a reduced size of the overall package structure, and also eliminates the need of bonding wires, thereby reducing the resistance, improving the electrical performance and avoiding signal distortions during transmission. Therefore, flip-chip mounting technology has currently become a popular technology for mounting chips to other electronic components.
Further, along with the miniaturization of electronic products, the minimum line width and pitch in a wafer process can reach 40 nm and even 28 nm. However, electromagnetic noise or inductive effects can easily occur in a fine-pitch semiconductor chip, thus adversely affecting the electrical performance of the semiconductor chip. Accordingly, after circuit layout of the chip is completed, a low-k dielectric layer, which typically has a dielectric constant k less than 3.9, is formed to cover the chip so as to improve the electrical performance and address the above-described problems of electromagnetic noise or inductive effects.
However, the low-k dielectric layer has a high coefficient of thermal expansion (CTE) and a low elastic modulus and is generally brittle. Therefore, it is more sensitive to thermal stress than other materials. Furthermore, due to a large difference between the coefficients of thermal expansion of the low-k dielectric layer and the chip material, high thermal stress can occur under heat, which can easily cause circuit or interface delamination or cracking.
Accordingly, Taiwan Patent No. I309464 proposes a solution to overcome the above-described problems. However, the proposed solution requires an additional carrier board such that the chip can be disposed in a cavity of the carrier board, thereby greatly increasing the overall fabrication cost and time.
Therefore, there is a need to provide a semiconductor structure and a fabrication method thereof that can avoid high thermal stress during flip-chip processing, thereby improving the product yield and reducing the fabrication cost and time.